Wafer level light-emitting diode array

ABSTRACT

A wafer level light-emitting diode (LED) array includes: a growth substrate; a plurality of LEDs arranged over the substrate, each including a first semiconductor layer, an activation layer, and a second semiconductor layer; a plurality of upper electrodes formed from a common material and electrically connected to the first semiconductor layers of the corresponding LEDs; and first and second pads arranged over the upper electrodes. The LEDs are connected in series by the upper electrodes, the first pad is electrically connected to an input LED from among the LEDs connected in series, and the second pad is electrically connected to an output LED from among the LEDs connected in series. Accordingly, a flip chip-type LED array can be provided which can be driven with a high voltage.

CROSS REFERENCE TO RELATED APPLICATION

This patent document is a 35 U.S.C. 371 National Stage application of PCT Application No. PCT/KR2013/007105, filed on Aug. 6, 2013, which further claims the benefits and priorities of prior Korean Patent Application No. 10-2012-0099263, filed on Sep. 7, 2012, prior Korean Patent Application No. 10-2012-0101716, filed on Sep. 13, 2012, prior Korean Patent Application No. 10-2013-0088712, filed on Jul. 26, 2013, and prior Korean Patent Application No. 10-2013-0088714, filed on Jul. 26, 2013. The entire disclosures of the above applications are incorporated by reference in their entirety as part of this document.

TECHNICAL FIELD

The present invention relates to a light emitting diode array, and more particularly, to a light emitting diode array with a plurality of light emitting diodes connected through wires and formed into a flip chip type.

BACKGROUND ART

A light emitting diode is a device for performing a light emitting operation when a voltage of a turn-on voltage or more is applied thereto through anode and cathode terminals thereof. Generally, the turn-on voltage for causing the light emitting diode to emit light has a value much lower than the voltage of a common power source. Therefore, the light emitting diode has a disadvantage in that it cannot be used directly under the common AC power source of 110V or 220V. The operation of the light emitting diode using the common AC power source requires a voltage converter for lowering the supplied AC voltage. Accordingly, a driving circuit for the light emitting diode should be provided, which becomes one factor causing fabrication costs of an illuminating apparatus including the light emitting diode to be increased. Since a discrete driving circuit should be provided, the volume of the illuminating apparatus is increased and unnecessary heat is generated. In addition, there are problems such as improvement of a power factor for the supplied power.

To use the common AC power source in a state where a discrete voltage converting means is excluded, there has been suggested a method of constructing an array by connecting a plurality of light emitting diode chips in series to one another. To implement the light emitting diodes as an array, the light emitting diode chips should be formed into individual packages. Thus, a substrate separating process, a packaging process for a separated light emitting diode chip, and the like are required, and a mounting process of arranging the packages on an array substrate and a wiring process for forming wirings between electrodes of the packages are additionally required. Therefore, there are problems in that a processing time for constructing the array is increased, and fabrication costs of the array are increased.

Moreover, wire bonding is used for the wiring process of forming the array, and a molding layer for protecting bonding wires is additionally formed on an entire surface of the array. Accordingly, there is a problem in that a molding process of forming the molding layer is additionally required, resulting in increase in the complexity of processes. Particularly, in a case of application of a chip type with a lateral structure, the light-emitting performance of the light emitting diode chip is lowered, and the quality of the light emitting diode is deteriorated due to the generation of heat.

In order to solve the aforementioned problems, there has been proposed a light emitting diode chip array in which an array including a plurality of light emitting diode chips is fabricated as a single package.

In Korean Patent Laid-Open Publication No. 2007-0035745, a plurality of lateral type light emitting diode chips are electrically connected on a single substrate through metal wiring formed using an air bridge process. According to this laid-open publication, there is an advantage in that a discrete packaging process is not required for each of the individual chips, and an array is formed on a wafer level. However, the air bridge connection structure results in weak durability and the lateral type causes a problem of deterioration of the light-emitting performance or heat-dissipating performance.

In U.S. Pat. No. 6,573,537, a plurality of flip-chip type light emitting diodes is formed on a single substrate. However, n- and p-electrodes of each of the light emitting diodes are exposed to the outside in a state where the n- and p-electrodes are separated from each other. Therefore, a wiring process of connecting a plurality of electrodes to one another should be added in order to use a single power source. To this end, a submount substrate is used in the US patent. That is, the flip-chip type light emitting diodes should be mounted on a discrete submount substrate for wiring between the electrodes. At least two electrodes for electrical connection with another substrate should be formed on a back surface of the submount substrate. In the US patent, since the flip-chip type light emitting diodes are used, there is an advantage of improvement of the light-emitting performance and heat-dissipating performance. On the contrary, the use of the submount substrate causes increase in both fabrication costs and the thickness of a final product. In addition, there are further disadvantages of needs for an additional wiring process for the submount substrate and an additional process of mounting the submount substrate on a new substrate.

Korean Patent Laid-Open Publication No. 2008-0002161 discloses a configuration in which flip-chip type light emitting diodes are connected in series to one another. According to the laid-open patent publication, a packaging process on a chip basis is not required, and the use of the flip-chip type light emitting diodes exhibits an effect of improvement of the light-emitting performance and heat-dissipating performance. However, a discrete reflective layer is used in addition to wiring between n-type and p-type semiconductor layers, and interconnection wiring is used on the n-type electrode. Therefore, a plurality of patterned metal layers should be formed. To this end, various kinds of masks should be used, which becomes a problem. In addition, exfoliation or crack occurs due to a difference in thermal expansion coefficient between the n-electrode and the interconnection electrode, or the like, and therefore, there is a problem in that electrical contact therebetween is opened.

DISCLOSURE OF INVENTION Technical Problem

An object of the present invention is to provide a flip-chip type light emitting diode array that can be driven at a high voltage.

Another object of the present invention is to provide a light emitting diode array that can be mounted directly on a printed circuit board or the like without any submount substrate.

A further object of the present invention is to provide a flip-chip type light emitting diode array that can prevent light loss without using a discrete reflective metal layer in addition to wires for connecting a plurality of light emitting diodes.

A still further object of the present invention is to provide a light emitting diode array that can prevent cracks from occurring in layers covering light emitting diodes, thereby improving the reliability thereof.

Other features and advantages of the present invention will be apparent and also better understood from the following description.

Technical Solution

A light emitting diode array according to an embodiment of the present invention includes a growth substrate; a plurality of light emitting diodes arranged on the substrate, wherein each of the plurality of light emitting diodes has a first semiconductor layer, an active layer and a second semiconductor layer; a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, wherein each of the plurality of upper electrodes is electrically connected to the first semiconductor layer of a respective one of the light emitting diodes; and first and second pads arranged on the upper electrodes. At least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes. The light emitting diodes are connected in series by the upper electrodes. The first pad is electrically connected to an input light emitting diode among the light emitting diodes connected in series. The second pad is electrically connected to an output light emitting diode among the light emitting diodes connected in series.

Accordingly, there is provided a flip-chip type light emitting diode array that can be driven at a high voltage. Further, since the light emitting diodes are connected in series by the upper electrodes, it is not necessary to use a submount substrate for electrically connecting the light emitting diodes.

Each of the first and second pads may be positioned over at least two of the light emitting diodes. The first or second pad may be formed to occupy at least ⅓ and less than ½ of the entire area of the light emitting diode array. The first and second pads are formed to be relatively large, thereby enabling the light emitting diode array to be easily mounted on a printed circuit board or the like through soldering or the like and to be firmly mounted.

The first and second pads may be formed of an identical material in an identical process. Thus, the first and second pads can be positioned on an identical level.

Each of the first and second pads may includes a first layer comprising Ti, Cr or Ni; and a second layer formed on the first layer and comprising Al, Cu, Ag or Au. Moreover, the first or second pad may further include a pad barrier layer of a conductive material. Accordingly, it is possible to prevent diffusion of a metal material such as Sn from a solder or the like. Thus, it is possible to provide a light emitting diode array that can be safely mounted by the soldering. The pad barrier layer may include a layer of Cr, Ni, Ti, W, TiW, Mo, Pt or a composite thereof.

The light emitting diode array may further include a first interlayer insulating layers arranged between the light emitting diodes and the upper electrodes. The upper electrodes may be insulated from side surfaces of the light emitting diodes by the first interlayer insulating layer. The first interlayer insulating layer may cover the side surfaces of the light emitting diodes as well as regions between the light emitting diodes. The upper electrodes may be positioned on the first interlayer insulating layer and may cover most of the regions between the light emitting diodes. In a conventional case where linear wiring is used, the wiring hardly covers the regions between the light emitting diodes. On the contrary, the upper electrodes may cover at least 30%, at least 50% or even at least 90% of the regions between the light emitting diodes. However, since the upper electrodes are spaced apart from one another, the upper electrodes cover less than 100% of the regions between the light emitting diodes.

The upper electrodes may be formed to have relatively large areas in order to reduce resistance caused by the upper electrodes. Thus, it is possible to facilitate current distribution and to decrease a forward voltage of the light emitting diode array.

The light emitting diode array may further include lower electrodes respectively arranged on the second semiconductor layers of the light emitting diodes. The first interlayer insulating layer may expose a portion of the lower electrode on each of the light emitting diodes. The upper electrode(s) electrically connected to the second semiconductor layer of the adjacent light emitting diode may be connected to the exposed portion of the lower electrode through the first interlayer insulating layer. Each of the lower electrodes may include a reflective layer.

The light emitting diode array may further include a second interlayer insulating layer covering the upper electrodes. The second interlayer insulating layer may expose the lower electrode arranged on the second semiconductor layer of the input light emitting diode, and the upper electrode connected to the first semiconductor layer of the output light emitting diode. Meanwhile, each of the first and second pads may be connected to the lower and upper electrodes through the second interlayer insulating layer.

In some embodiments, each of the light emitting diodes may have a via hole for causing the first semiconductor layer to be exposed through the second semiconductor layer and the active layer. Each of the upper electrodes may be connected to the first semiconductor layer of a respective one of the light emitting diodes through the via hole.

Meanwhile, the upper electrodes may occupy at least 30% and less than 100% of the entire area of the light emitting diode array.

Each of the upper electrodes may be in the form of a plate or sheet having a ratio of length to width in a range of 1:3 to 3:1. Unlike a conventional linear wiring, since the upper electrodes are in the form of the plate or sheet, it is possible to facilitate current distribution and to decrease the forward voltage of the light emitting diode array.

At least one of the upper electrodes may have a length or width larger than that of a respective one of the light emitting diodes. Thus, the upper electrode can cover the region between the light emitting diodes, and can reflect light generated in the active layer toward the substrate.

Further, each of the light emitting diodes may be separated by a mesa-etched region exposing the substrate, and side surfaces of films exposed by mesa etching may have inclination angles of 10 to 60 degrees with respect to the substrate. Accordingly, it is possible to prevent cracks from being produced in the layers covering the mesa-etched region.

The light emitting diode array may further include a first interlayer insulating layers arranged between the light emitting diodes and the upper electrodes. The upper electrodes may include side surfaces having inclination angles of 10 to 45 degrees with respect to a surface of the first interlayer insulating layer. Accordingly, it is possible to prevent cracks from being produced in the layers covering the upper electrodes. The upper electrodes may have thicknesses in range of 2000 to 10000 Å.

The light emitting diode array may further include lower electrodes respectively arranged on the second semiconductor layers of the light emitting diodes. The first interlayer insulating layer may expose a portion of the lower electrode of each of the light emitting diodes. The upper electrode(s) electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes may be connected to the exposed lower electrode through the first interlayer insulating layer.

Each of the lower electrodes may include a side surface having an inclination angle of 10 to 45 degrees with a surface of the second semiconductor layer. Accordingly, it is possible to prevent cracks from being produced in the layers covering the lower electrodes. The thicknesses of the lower electrodes may be in a range of 2000 to 10000 Å.

The first interlayer insulating layer may include a side surface having an inclination angle of 10 to 60 degrees with respect to a surface of the exposed lower electrode. Accordingly, it is possible to cracks from being produced in the layers covering the first interlayer insulating layer. The first interlayer insulating layer may have a thickness of 2000 to 20000 Å.

Meanwhile, the light emitting diode array may further include a second interlayer insulating layer covering the upper electrodes. The second interlayer insulating layer may expose the lower electrode arranged on the second semiconductor of the input light emitting diode, and the upper electrode connected to the first semiconductor layer of the output light emitting diode. Each of the first and second pads may be connected to the lower and upper electrodes through the second interlayer insulating layer.

Moreover, the second interlayer insulating layer may include a side surface having an inclination angle of 10 to 60 degrees with respect to a surface of the upper electrode. Thus, it is possible to prevent cracks from being produced in the first and second pads covering the second interlayer insulating layer. The second interlayer insulating layer may have thickness of 2000 to 20000 Å.

Each of the light emitting diodes may have a via hole exposing a portion of the first semiconductor layer therethrough, and each of the upper electrodes may be connected to the first semiconductor layer of a corresponding light emitting diode through the via hole.

The side inclination angles of the layers exposed through the via hole may be in a range of 10 to 60 degrees. Accordingly, it is possible to prevent cracks from being produced in the layers covering the via hole.

Advantageous Effects

According to embodiments of the present invention, it is possible to provide a light emitting diode array on a wafer level, which can be driven at a high voltage and can be mounted directly on a printed circuit board or the like. In particular, since light emitting diodes of the light emitting diode array are connected in series by upper electrodes, a submount substrate is not required. Since the upper electrode can include an ohmic contact layer, it is not necessary to form a separate ohmic contact layer.

In addition, side surfaces of the light emitting diodes are formed to be inclined at a predetermined angle, so that it is possible to provide a flip-chip type light emitting diode array on a wafer level, which has improved reliability. Further, the side surfaces of the lower electrodes, first interlayer insulating layer, upper electrodes or second interlayer insulating layer are formed to be inclined at a predetermined angle, so that it is possible to prevent cracks from being produced in another layer formed on the respective layers.

Further, since the upper electrodes occupy a relatively large area, and also cover side surfaces of the light emitting diodes and most of the regions between the light emitting diodes, the upper electrodes can be used to reflect light. Thus, it is possible to reduce a loss of light generated in the regions between the light emitting diodes. Therefore, it is not necessary to additionally form a separate reflective metal layer for reflecting light, in addition to the upper electrodes.

Furthermore, the upper electrodes are made in the form of a plate or sheet having a wide area, thereby improve current distribution performance and decreasing a forward voltage at an identical current while using an identical number of light emitting diodes.

DESCRIPTION OF DRAWINGS

FIGS. 1 and 2 are plan and sectional views showing that a plurality of via holes are formed in a laminated structure according to an embodiment of the present invention.

FIGS. 3 and 4 are plan and sectional views showing that lower electrodes are formed on a second semiconductor layer of FIG. 1.

FIG. 5 is a plan view showing a state where cell regions are separated with respect to the structure of FIG. 3.

FIG. 6 is a sectional view taken along line A1-A2 in the plan view of FIG. 5.

FIG. 7 is a perspective view of the structure in the plan view of FIG. 5.

FIG. 8 is a plan view showing that a first interlayer insulating layer is formed on an entire surface of the structure of FIGS. 5 to 7, and portions of a first semiconductor layer and the lower electrodes are exposed in each of the cell regions.

FIGS. 9 to 12 are sectional views taken along specific lines in the plan view of FIG. 8.

FIG. 13 is a plan view showing that upper electrodes are formed on the structure illustrated in FIGS. 8 to 12.

FIGS. 14 to 17 are sectional views taken along specific lines in the plan view of FIG. 13.

FIG. 18 is a perspective view of the structure in the plan view of FIG. 13.

FIG. 19 is an equivalent circuit diagram obtained by modeling the structure of FIGS. 13 to 18 according to a preferred embodiment of the present invention.

FIG. 20 is a plan view showing that a second interlayer insulating layer is applied on an entire surface of the structure of FIG. 13, a portion of a first electrode in a first cell region is exposed, and a portion of a fourth lower electrode in a fourth cell region is exposed.

FIGS. 21 to 24 are sectional views taken along specific lines in the plan view of FIG. 20.

FIG. 25 is a plan view showing that first and second pads are formed in the structure of FIG. 20.

FIGS. 26 to 29 are sectional views taken along specific lines in the plan view of FIG. 25.

FIG. 30 is a perspective view taken along line C2-C3 in the plan view of FIG. 25.

FIG. 31 is a circuit diagram obtained by modeling a connection of ten light emitting diodes in series according to an embodiment of the present invention.

FIG. 32 is a circuit diagram obtained by modeling an array having light emitting diodes connected in series/parallel according to an embodiment of the present invention.

(Description of Reference Numerals) 100: substrate 111, 112, 113, 114: first semiconductor layer 121, 122, 123, 124: active layer 131, 132, 133, 134: second semiconductor layer 140: via hole 151: first lower electrode 152: second lower electrode 153: third lower electrode 154: fourth lower electrode 161: first cell region 162: second cell region 163: third cell region 164: fourth cell region 170: first interlayer insulating layer 181: first upper electrode 182: second upper electrode 183: third upper electrode 184: fourth upper electrode 190: second interlayer insulating layer 210: first pad 220: second pad

MODE FOR INVENTION

Hereinafter, preferred embodiments of the present invention will be described in greater detail with reference to the accompanying drawings, in order to more fully describe the present invention. However, the present invention is not limited to the following embodiments but may be implemented in other forms.

In these embodiments, it will be understood that the term “first”, “second”, “third” or the like does not impose any limitation on components but are only used to distinguish the components.

FIGS. 1 and 2 are plan and sectional views showing that a plurality of via holes are formed in a laminated structure according to an embodiment of the present invention.

In particular, FIG. 2 is a sectional view taken along line A1-A2 in the plan view of FIG. 1.

Referring to FIGS. 1 and 2, a first semiconductor layer 110, an active layer 120 and a second semiconductor layer 130 are formed on a substrate 100, and via holes 140 are formed to allow a surface of the semiconductor layer 110 to be exposed therethrough.

The substrate 100 comprises a material such as sapphire, silicon carbide or GaN. Any material may be used for the substrate 100 as long as it can induce the growth of a thin film to be formed on the substrate 100. The first semiconductor layer 110 may have n-type conductivity. The active layer 120 may have a multiple quantum well structure, and the second semiconductor layer 130 is formed on the active layer 120. When the first semiconductor layer 110 has the n-type conductivity, the second semiconductor layer 130 has p-type conductivity. A buffer layer (not shown) may be further formed between the substrate 100 and the first semiconductor layer 110 so as to facilitate single crystalline growth of the first semiconductor layer 110.

Subsequently, selective etching is performed on the structure formed with up to the second semiconductor layer 130, and a plurality of via holes 140 are formed. Portions of the lower first semiconductor layer 110 are exposed through the via holes 140. The via holes 140 may be formed through a conventional etching process. For example, a photoresist is applied, and portions of the photoresist on regions where the via holes will be formed are then removed through a conventional patterning process to form a photoresist pattern. Thereafter, an etching process is performed by using the photoresist pattern as an etching mask. The etching process is performed until the portions of the first semiconductor layer 110 are exposed. After the etching process, the photoresist pattern remaining is removed.

The via holes 140 have a range of inclination angles (a) with respect to a surface of the substrate or a surface of the first semiconductor layer 110, which is exposed by performing the etching process. In particular, if the via holes 140 do not have a range of inclination angles, in a subsequent process of vapor-depositing a metal or applying an insulation material, cracks may be produced in a deposited metal layer or applied insulation material layer. Even though no crack is produced in a fabrication process, a problem of reliability is caused when a light emitting diode is used later. Heat and electrical stress generated when the light emitting diode emits light according to the supply of electrical power cause cracks to be produced in metal or insulation material layers formed on the via holes 140 beyond the particular inclination angle (a). The produced cracks cause malfunction of the light emitting diode and thus a decrease in luminance.

It is preferable that the via holes 140 have an angle of 10 to 60 degrees with respect to the surface of the substrate 100 or the surface of the first semiconductor layer 110.

If the inclination angle (a) is less than 10 degrees, the area of the active layer 120 is decreased due to an excessively low slope. The decrease in the area of the active layer causes a decrease in luminance. The substantial area of the second semiconductor layer 130 is much smaller than that of the first semiconductor layer 110. Generally, the semiconductor layer 130 has p-type conductivity, and the first semiconductor layer 110 has n-type conductivity. When the light emitting diode emits light, the first semiconductor layer 110 supplies electrons to the active layer 120, and the second semiconductor layer 130 supplies holes to the active layer 120. The improvement of light-emitting efficiency tends to rely on the uniform and smooth supply of holes rather than the supply of electrons. Thus, an excessive decrease in the area of the second semiconductor layer 130 may cause the light-emitting efficiency to be lowered. In a case where the inclination angle (a) exceeds 60 degrees, cracks may be produced in a subsequent metal or insulation material layer due to a high slope.

Meanwhile, the shape and number of the via holes 140 may be variously changed.

FIGS. 3 and 4 are plan and sectional views showing that lower electrodes are formed on the second semiconductor layer of FIG. 1. Particularly, FIG. 4 is a sectional view taken along line A1-A2 in the plan view of FIG. 3.

Referring to FIGS. 3 and 4, the lower electrodes 151, 152, 153 and 154 are formed in regions except the via holes 140, and a plurality of cell regions 161, 162, 163 and 164 may be defined by the formation of the lower electrodes 151, 152, 153 and 154. The lower electrodes 151, 152, 153 and 154 may be formed by employing a lift-off process used upon formation of a metal electrode. For example, a photoresist is formed in separating regions excluding the virtual cell regions 161, 162, 163 and 164 and in the regions in which the via holes 140 are formed, and a metal layer is formed through conventional thermal deposition or the like. Subsequently, the photoresist is removed, thereby forming the lower electrodes 151, 152, 153 and 154 on the second semiconductor layer 130. Any material may be employed for the lower electrodes 151, 152, 153 and 154 as long as it is a metallic material capable of being in ohmic contact with the second semiconductor layer 130. The lower electrodes 151, 152, 153 and 154 may comprise Ni, Cr or Ti, and may be composed of a composite metal layer of Ti/Al/Ni/Au.

The lower electrodes 151, 152, 153 and 154 may have thicknesses in a range of 2000 to 10000 Å. If the thicknesses of the lower electrodes 151, 152, 153 and 154 are less than 2000 Å, the reflection of light from the lower electrodes 151, 152, 153 and 154 toward the substrate 100 is not smooth, and there is a leakage of light transmitted through the lower electrodes 151, 152, 153 and 154 in the form of thin films. If the thicknesses of the lower electrodes 151, 152, 153 and 154 exceed 10000 Å, there is a problem in that it takes an excessive amount of time to perform a process of forming the lower electrodes, such as thermal deposition.

The lower electrodes 151, 152, 153 and 154 may have inclination angles (b) of 10 to 45 degrees with respect to the surface of the second semiconductor layer 130. If the inclination angles (b) of the lower electrodes 151, 152, 153 and 154 are less than 10 degrees, the efficiency of reflection of light is lowered due to a very gentle slope. In addition, there is a problem in that the uniformity of thickness on the surface of the lower electrode cannot be ensured due to a low inclination angle. If the inclination angles (b) of the lower electrodes 151, 152, 153 and 154 exceed 45 degrees, cracks may be produced in a subsequent layer due to a high inclination angle.

The adjustment of the inclination angles (b) of the lower electrodes 151, 152, 153 and 154, which are defined with respect to the surface of the second semiconductor layer 130, can be achieved by means of changes in disposition of the substrate and the angle of the substrate with respect to the advancing direction of metal atoms in a process such as thermal deposition.

In FIGS. 3 and 4, the regions in which the four lower electrodes 151, 152, 153 and 154 are formed define four cell regions 161, 162, 163 and 164, respectively. The second semiconductor layer 130 is exposed in spaces among the cell regions 161, 162, 163 and 164. The number of the cell regions 161, 162, 163 and 164 may correspond to that of light emitting diodes included in an array to be formed. Therefore, the number of the cell regions may be variously changed.

Although FIG. 4 shows that the lower electrode 151, 152, 153 or 154 is discrete in the same cell region 161, 162, 163 or 164, this is a phenomenon occurring as line A1-A2 transverses the via holes 140. As can be seen in FIG. 3, the lower electrode 151, 152, 153 or 154 formed in the same cell region is physically continuous. Thus, the lower electrode 151, 152, 153 or 154 formed in the same cell region is in an electrically short-circuited state even though the via holes 140 are formed therein.

FIG. 5 is a plan view showing a state where cell regions are separated with respect to the structure of FIG. 3, FIG. 6 is a sectional view taken along line A1-A2 in the plan view of FIG. 5, and FIG. 7 is a perspective view of the structure in the plan view of FIG. 5.

Referring to FIGS. 5, 6 and 7, mesa-etched regions are formed through mesa etching for the spaces among the four cell regions 161, 162, 163 and 164. The substrate 100 is exposed in the mesa-etched regions formed through the mesa etching. Thus, the four cell regions 161, 162, 163 and 164 are electrically completely separated from one another. If a buffer layer is interposed between the substrate 100 and the first semiconductor layer 110 in FIGS. 1 to 4, the buffer layer may remain even in the separation process of the cell regions 161, 162, 163 and 164. However, in order to completely separate the cell regions 161, 162, 163 and 164 from one another, the buffer layer between adjacent ones of the cell regions 161, 162, 163 and 164 may be removed through the mesa etching.

Side surfaces of the first semiconductor layer 110, the active layer 120, the second semiconductor layer 130 and the lower electrodes 151, 152, 153 and 154 are exposed on side surfaces of the mesa regions by means of the mesa etching. The exposed side surfaces may have inclination angles (c) of 10 to 60 degrees with respect to the surface of the substrate 100. The adjustment of the inclination angles (c) of the exposed side surfaces can be achieved by adjusting the angle of the substrate with respect to the advancing direction of an etchant.

If the inclination angles (c) of films exposed by means of the mesa etching are less than 10 degrees, a decrease in light-emitting area is caused due to a low inclination angle, and light efficiency may be lowered. If the inclination angle (c) exceeds 60 degrees, the thickness of a film formed later may be ununiform or cracks may be produced in the film due to a high inclination angle. This becomes a factor in deterioration of the reliability of a device.

The range of the inclination angles (c) of the films exposed through the mesa etching has influence on the reflection of light caused by a metal layer formed in a subsequent process. For example, the metal layer is formed on sidewalls of the films exposed through the mesa etching. If the inclination angle (c) is less than 10 degrees, light formed in the active layer is not reflected in a predetermined range with respect to the substrate but scattered. Even though the inclination angle (c) exceeds 60 degrees, the reflection of light is not progressed toward a predetermined region but scattered.

With the separation process between adjacent ones of the cell regions 161, 162, 163 and 164, first semiconductor layers 111, 112, 113 and 114, active layers 121, 122, 123 and 124, second semiconductor layers 131, 132, 133 and 134 and lower electrodes 151, 152, 153 and 154 are independently formed in the cell regions 161, 162, 163 and 164, respectively. Thus, the first lower electrode 151 is exposed in the first cell region 161, and the first semiconductor layer 111 is exposed through the via holes 140. The second lower electrode 152 is exposed in the second cell region 162, and the first semiconductor layer 112 is exposed through the via holes 140. Similarly, the third lower electrode 153 and the first semiconductor layer 113 are exposed in the third cell region 163, and the fourth lower electrode 154 and the first semiconductor layer 114 are exposed in the fourth cell region 164.

In the present invention, the light emitting diode refers to a structure in which the first semiconductor layer 111, 112, 113 or 114, the active layer 121, 122, 123 or 124 and the second semiconductor layer 131, 132, 133 or 134 are laminated, respectively. Thus, one light emitting diode is formed in one cell region. When the light emitting diode is modeled such that the first semiconductor layer 111, 112, 113 or 114 has n-type conductivity and the second semiconductor layer 131, 132, 133 or 134 has p-type conductivity, the lower electrode 151, 152, 153 or 154 formed on the second semiconductor layer 131, 132, 133 or 134 may be referred to as an anode electrode of the light emitting diode.

FIG. 8 is a plan view showing that a first interlayer insulating layer is formed on an entire surface of the structure of FIGS. 5 to 7, and portions of a first semiconductor layer and the lower electrodes are exposed in each of the cell regions.

Moreover, FIGS. 9 to 12 are sectional views taken along specific lines in the plan view of FIG. 8. Particularly, FIG. 9 is a sectional view taken along line B1-B2 in the plan view of FIG. 8, FIG. 10 is a sectional view taken along line C1-C2 in the plan view of FIG. 8, FIG. 11 is a sectional view taken along line D1-D2 in the plan view of FIG. 8, and FIG. 12 is a sectional view taken along line E1-E2 in the plan view of FIG. 8.

First, a first interlayer insulating layer 170 is formed with respect to the structure of FIGS. 5 to 7. Moreover, portions of the lower electrodes 151, 152, 153 and 154 and of the first semiconductor layers 111, 112, 113 and 114 under the via holes are exposed by means of patterning.

For example, in the first cell region 161, two pre-formed via holes are opened so that portions of the first semiconductor layer 111 are exposed, and a portion of the first lower electrode 151 formed on the pre-formed second semiconductor layer 131 is exposed. In the second cell region 162, portions of the first semiconductor layer 112 are exposed through the pre-formed via holes, and a portion of the second lower electrode 152 is exposed by means of etching for a portion of the first interlayer insulating layer 170. In the third cell region 163, portions of the first semiconductor layer 113 are exposed through the via holes, and a portion of the third lower electrode 153 is exposed by means of etching for a portion of the first interlayer insulating layer 170. In the fourth cell region 164, portions of the first semiconductor layer 114 are exposed through the via holes, and a portion of the fourth lower electrode 154 is exposed by means of etching for a portion of the first interlayer insulating layer 170.

As a result, in FIGS. 8 to 12, the first interlayer insulating layer 170 is formed on the entire surface of the substrate, and the portions of the first semiconductor layers 111, 112, 113 and 114 under the via holes and the portions of the lower electrodes 151, 152, 153 and 154 on the second semiconductor layers 131, 132, 133 and 134 are exposed in each of the cell regions 161, 162, 163 and 164 by means of selective etching. The remaining region is shielded by the first interlayer insulating layer 170.

The first interlayer insulating layer 170 may be formed of an insulating material having a light transmittance. For example, the first interlayer insulating layer may comprise SiO₂.

Furthermore, the first interlayer insulating layer 170 may have a thickness of 2000 to 20000 Å.

If the thickness of the first interlayer insulating layer 170 is less than 2000 Å, it is difficult to secure an insulation property due to a small thickness. In particular, if the first interlayer insulating layer 170 is formed on the sidewalls of the mesa-etched regions or the via holes 140, the first interlayer insulating layer 170 has a certain slope, so that the insulation of the first interlayer insulating layer 170 may be broken down.

If the thickness of the first interlayer insulating layer 170 exceeds 20000 Å, it is difficult to perform selective etching on the first interlayer insulating layer 170. For example, portions of the lower electrodes and the first semiconductor layer should be exposed in the via holes 140. To this end, a process of applying the first interlayer insulating layer 170 to the entire surface and a selective etching process are performed. The application of a photoresist and patterning are performed for the selective etching process. Etching is performed for regions opened by a residual photoresist pattern. If the thickness of the first interlayer insulating layer 170 exceeds 20000 Å, the photoresist pattern to be used as an etching mask may also be removed in the process of selectively etching the first interlayer insulating layer 170. Therefore, the etching may be performed on an undesired portion, resulting in an error in the process.

The first interlayer insulating layer 170 may have an inclination angle (d) of 10 to 60 degrees with respect to the surface of the lower electrode exposed by the selective etching.

If the inclination angle d of the first interlayer insulating layer 170 is less than 10 degrees, the area of the exposed surface of the lower electrode decreases or the substantial thickness of the first interlayer insulating layer 170 decreases. Therefore, there is a problem in that it is difficult to secure an insulation property. That is, the first interlayer insulating layer 170 functions to electrically insulate the lower electrode from another conductive film formed thereon. Therefore, the first interlayer insulating layer 170 should have a sufficient thickness, and the lower electrode should be exposed with a certain area for the purpose of additional electrical connection. If the first interlayer insulating layer 170 has a very low slope, the exposed area of the lower electrode should be decreased to implement the first interlayer insulating layer 170 of a certain thickness. In a case where it is intended to secure the area of the exposed lower electrode beyond a predetermined value, the insulation of the first interlayer insulating layer 170 with the small thickness may be broken down due to a low slope.

If the inclination angle (d) of the first interlayer insulating layer 170 exceeds 60 degrees, there is a problem in that the quality of another film to be formed on the first interlayer insulating layer 170 may be deteriorated due to a large inclination angle.

The adjustment of the inclination angle of the first interlayer insulating layer 170 can be achieved by adjusting the angle of etching in a partial etching process for the first interlayer insulating layer 170 formed on the lower electrode.

FIG. 13 is a plan view showing that upper electrodes are formed on the structure illustrated in FIGS. 8 to 12, and FIGS. 14 to 17 are sectional views taken along specific lines in the plan view of FIG. 13. Particularly, FIG. 14 is a sectional view taken along line B1-B2 in the plan view of FIG. 13, FIG. 15 is a sectional view taken along line C1-C2 in the plan view of FIG. 13, FIG. 16 is a sectional view taken along line D1-D2 in the plan view of FIG. 13, and FIG. 17 is a sectional view taken along line E1-E2 in the plan view of FIG. 13.

Referring to FIG. 13, upper electrodes 181, 182, 183 and 184 are formed. The upper electrodes 181, 182, 183 and 184 are formed as four discrete regions. For example, the first upper electrode 181 is formed over the first cell region 161 and a portion of the second cell region 162. The second upper electrode 182 is formed over a portion of the second cell region 162 and a portion of the third cell region 163. The third upper electrode 183 is formed over a portion of the third cell region 163 and a portion of the fourth cell region 164. The fourth upper electrode 184 is formed in a portion of the fourth cell region 164. Thus, each of the upper electrodes 181, 182, 183 and 184 is formed while shielding spaces between adjacent ones of the cell regions. The upper electrodes 181, 182, 183 and 184 may cover no less than 30%, even no less than 50%, or no less than 90% of the spaces between the adjacent cell regions. However, since the upper electrodes 181, 182, 183 and 184 are spaced apart from one another, the upper electrodes 181, 182, 183 and 184 cover less than 100% of regions between adjacent ones of light emitting diodes. The entire of the upper electrodes 181, 182, 183 and 184 may occupy no less than 30%, even no less than 50%, or no less than 90% of the entire area of the light emitting diode array. However, since the upper electrodes 181, 182, 183 and 184 are spaced apart from one another, they occupy less than 100% of the entire area of the light emitting diode array. Each of the upper electrodes 181, 182, 183 and 184 has the shape of a plate or sheet having a ratio of length and width ranging from 1:3 to 3:1. Further, at least one of the upper electrodes 181, 182, 183 and 184 has a length or width greater than that of a corresponding light emitting diode (cell region).

Referring to FIG. 14, the first upper electrode 181 is formed on the first interlayer insulating layer 170 in the first cell region 161, and is formed on portions of the first semiconductor layer 111 opened through the via holes. In addition, the first upper electrode 181 allows a portion of the first lower electrode 151 to be exposed in the first cell region 161 and is formed on a portion of the second lower electrode 152 exposed in the second cell region 162.

The second upper electrode 182 is formed on portions of the first semiconductor layer 112 exposed through the via holes in the second cell region 162 in a state in which the second upper electrode 182 is physically separated from the first upper electrode 181. In addition, the second upper electrode 182 is formed on the first interlayer insulating layer 170.

In FIG. 14, the first upper electrode 181 electrically connects the first semiconductor layer 111 in the first cell region 161 to the second semiconductor layer 132 in the second cell region 162. Despite of the presence of the via holes, the second lower electrode 152 in the second cell region 162 is entirely in an electrically short-circuited state in one cell region. Thus, the first semiconductor layer 111 in the first cell region 161 is electrically connected to the second semiconductor layer 132 in the second cell region 162 through the second lower electrode 152.

In FIG. 15, the second upper electrode 182 is formed on portions of the first semiconductor layer 112 exposed through the via holes in the second cell region 162, and is formed to extend to the third lower electrode 153 in the third cell region 163.

The third upper electrode 183 physically separated from the second upper electrode 182 is also formed on portions of the first semiconductor layer 113 exposed through the via holes in the third cell region 163.

In FIG. 15, the second upper electrode 182 is electrically connected to the portions of the first semiconductor layer 112 through the via holes in the second cell region 162, and is electrically connected to the third lower electrode 153 in the third cell region 163. Thus, the first semiconductor layer 112 in the second cell region 162 can maintain the same potential as the second semiconductor layer 133 in the third cell region 163.

Referring to FIG. 16, the third upper electrode 183 is formed on portions of the first semiconductor layer 113 exposed through the via holes in the third cell region 163, and is formed to extend to the fourth lower electrode 154 in the fourth cell region 164. Thus, the first semiconductor layer 113 in the third cell region 163 is electrically connected to the second semiconductor layer 134 in the fourth cell region 164.

The fourth upper electrode 184 physically separated from the third upper electrode 183 is electrically connected to the portions of the first semiconductor layer 114 exposed through the via holes in the fourth cell region 164.

Referring to FIG. 17, the fourth upper electrode 184 is formed on portions of the first semiconductor layer 114 exposed through the via holes in the fourth cell region 164. The first upper electrode 181 physically separated from the fourth upper electrode 184 is formed on portions of the first semiconductor layer 111 exposed through the via holes in the first cell region 161, and allows a portion of the first lower electrode 151 to be exposed in the first cell region 161.

The contents disclosed in FIGS. 13 to 17 will be summarized below. The first semiconductor layer 111 in the first cell region 161 and the second semiconductor layer 132 in the second cell region 162 establish the same potential through the first upper electrode 181. The first semiconductor layer 112 in the second cell region 162 and the second semiconductor layer 133 in the third cell region 163 establish the same potential through the second upper electrode 182. The first semiconductor layer 113 in the third cell region 163 establish the same potential as the second semiconductor layer 134 in the fourth cell region 164 through the third upper electrode 183. The first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first cell region 161 is exposed.

Of course, the same potential is established by assuming ideal electrical connection in a state where resistances of the upper electrodes 181, 182, 183 and 184 and contact resistances between the upper electrodes 181, 182, 183 and 184 and the lower electrodes 151, 152, 153 and 154 are neglected. Thus, in the operation of an actual device, a voltage drop may be sometimes caused by resistance components of the upper electrodes 181, 182, 183 and 184 and the lower electrodes 151, 152, 153 and 154, which are kinds of metal wires.

The upper electrodes 181, 182, 183 and 184 may be formed of any of materials that can be in ohmic contact with the first semiconductor layers 111, 112, 113 and 114. In addition, any material may be used for the upper electrodes 181, 182, 183 and 184 as long as it is a material that can be in ohmic contact with the lower electrodes 151, 152, 153 and 154 made of a metallic material. Thus, the upper electrodes 181, 182, 183 and 184 may include, as an ohmic contact layer, a metal layer comprising Ni, Cr, Ti, Rh or Al; or a conductive oxide layer such as an ITO layer.

The upper electrodes 181, 182, 183 and 184 may include a reflective layer of Al, Ag, Rh or Pt in order to reflect light, which is generated from the active layers 121, 122, 123 and 124 in the respective cell regions 161, 162, 163 and 164, toward the substrate 100. In particular, the light generated from the respective active layers 121, 122, 123 and 124 is reflected from the lower electrodes 151, 152, 153 and 154 toward the substrate 100. In addition, light transmitted through the spaces between the adjacent ones of the cell regions 161, 162, 163 and 164 is reflected by the upper electrodes 181, 182, 183 and 184 shielding the spaces between the adjacent ones of the cell regions 161, 162, 163 and 164.

The thicknesses of the upper electrodes 181, 182, 183 and 184 may be in a range of 2000 to 10000 Å. If the thicknesses of the upper electrode 181, 182, 183 and 184 are less than 2000 Å, the reflection of the light from the upper electrodes 181, 182, 183 and 184 toward the substrate 100 is not smooth, and there is a leakage of light transmitted through the upper electrodes 181, 182, 183 and 184 in the form of thin films. If the thicknesses of the upper electrode 181, 182, 183 and 184 exceed 10000 Å, there is a problem in that it takes an excessive amount of time to form the upper electrodes by means of thermal deposition or the like.

Further, the upper electrodes 181, 182, 183 and 184 may have inclination angles (e) of 10 to 45 degrees with respect to the surface of the first interlayer insulating layer 170. If the inclination angles (e) of the upper electrodes 181, 182, 183 and 184 are less than 10 degrees, the efficiency of the reflection of light is lowered due to a very gentle slope. In addition, there is a problem in that the uniformity of thickness on the surface of the upper electrode cannot be secured due to a small inclination angle. If the inclination angles (e) of the upper electrodes 181, 182, 183 and 184 exceed 45 degrees, cracks may be produced in a subsequent layer due to a large inclination angle.

The adjustment of the inclination angles (e) of the upper electrodes 181, 182, 183 or 184, which are defined with respect to the surface of the first interlayer insulating layer 170, can be achieved by means of changes in disposition of the substrate and the angle of the substrate with respect to the advancing direction of metal atoms in a process such as thermal deposition.

If the first semiconductor layers 111, 112, 113 and 114 have n-type conductivity and the second semiconductor layers 131, 132, 133 and 134 have p-type conductivity, each of the upper electrodes may be modeled as a cathode electrode of the light emitting diode, and simultaneously as wiring for connecting the cathode electrode of the light emitting diode to the lower electrode that is an anode electrode of a light emitting diode formed in an adjacent cell region. That is, in the light emitting diode formed in the cell region, the upper electrode may be modeled to form a cathode electrode and simultaneously to be wiring for electrically connecting the cathode electrode of the light emitting diode to an anode electrode of a light emitting diode in an adjacent cell region.

FIG. 18 is a perspective view of the structure in the plan view of FIG. 13.

Referring to FIG. 18, the first to third upper electrodes 181 to 183 are formed over at least two cell regions. The space between adjacent cell regions is shielded. The upper electrodes allow light, which may be leaked between adjacent cell regions, to be reflected through the substrate, and are electrically connected to the first semiconductor layer in each cell region. The upper electrodes are electrically connected to the second semiconductor layer in an adjacent cell region.

FIG. 19 is an equivalent circuit diagram obtained by modeling the structure of FIGS. 13 to 18 according to an embodiment of the present invention.

Referring to FIG. 19, four light emitting diodes D1, D2, D3 and D4 and a wiring relationship among the light emitting diodes are shown.

The first light emitting diode D1 is formed in the first cell region 161, the second light emitting diode D2 is formed in the second cell region 162, the third light emitting diode D3 is formed in the third cell region 163, and the fourth light emitting diode D4 is formed in the fourth cell region 164. The first semiconductor layers 111, 112, 113 and 114 in the cell regions 161, 162, 163 and 164 are modeled as n-type semiconductors, and the second semiconductor layers 131, 132, 133 and 134 are modeled as p-type semiconductors.

The first upper electrode 181 is electrically connected to the first semiconductor layer 111 in the first cell region 161 and extends to the second cell region 162 so as to be electrically connected to the second semiconductor layer 132 in the second cell region 162. Thus, the first upper electrode 181 is modeled as wiring for connecting a cathode terminal of the first light emitting diode D1 to an anode electrode of the second light emitting diode D2.

The second upper electrode 182 is modeled as wiring for connection between a cathode terminal of the second light emitting diode D2 and an anode terminal of the third light emitting diode D3. The third upper electrode 183 is modeled as wiring for connection between a cathode electrode of the third light emitting diode D3 and an anode terminal of the fourth light emitting diode D4. The fourth upper electrode 184 is modeled as wiring for forming a cathode electrode of the fourth light emitting diode D4.

Thus, the anode terminal of the first light emitting diode D1 and the cathode terminal of the fourth light emitting diode D4 are in an electrically opened state with respect to an external power source, and the other light emitting diodes D2 and D3 are electrically connected in series. In order to perform a light-emitting operation, the anode terminal of the first light emitting diode D1 should be connected to a positive power voltage V+, and the cathode terminal of the fourth light emitting diode D4 should be connected to a negative power voltage V−. Thus, the light emitting diode connected to the positive power voltage V+ can be referred to as an input light emitting diode, and the light emitting diode connected to the negative power voltage V− can be referred to as an output light emitting diode.

In the connection relationships among the plurality of light emitting diodes configured as described above, a cell region in which the cathode terminal connected to the negative power voltage V− is formed is provided with an upper electrode for shielding only a portion of the corresponding cell region. A cell region in which another connection relationship is established is provided with an upper electrode for making a shield between cell regions electrically connected to each other.

FIG. 20 is a plan view showing that a second interlayer insulating layer is applied on an entire surface of the structure of FIG. 13, a portion of the first electrode in the first cell region is exposed, and a portion of the fourth lower electrode in the fourth cell region is exposed.

Referring to FIG. 20, with a second interlayer insulating layer 190, the upper electrodes are shielded, and a portion of the first lower electrode 151 and a portion of the fourth upper electrode 184 are exposed. This means that, in FIG. 19, only the anode terminal of the first light emitting diode D1 is exposed and only the cathode terminal of the fourth light emitting diode D4 is exposed.

FIG. 21 is a sectional view taken along line B1-B2 in the plan view of FIG. 20, FIG. 22 is a sectional view taken along line C1-C2 in the plan view of FIG. 20, FIG. 23 is a sectional view taken along line D1-D2 in the plan view of FIG. 20, and FIG. 24 is a sectional view taken along line E1-E2 in the plan view of FIG. 20.

Referring to FIG. 21, in the first cell region 161, portions of the first lower electrode 151 electrically connected to the second semiconductor layer 131 are opened. The remaining portions in the first cell region are covered with the second interlayer insulating layer 190 that is also over the second cell region 162.

Referring to FIG. 22, the second and third cell regions 162 and 163 are completely covered with the second interlayer insulating layer 190.

Referring to FIGS. 23 and 24, portions of the fourth upper electrode 184 in the fourth cell region 164 are exposed, and portions of the first lower electrode 151 in the first cell region 161 are exposed.

The exposure of the fourth upper electrode 184 and the first lower electrode 151 is performed by selective etching for the second interlayer insulating layer 190.

The second interlayer insulating layer 190 is selected from an insulation material capable of protecting an underlying film from an external environment. In particular, the second interlayer insulating layer may comprise SiN or the like that has an insulation property and can block a change in temperature or humidity.

The thickness of the second interlayer insulating layer 190 may be in a predetermined range. For example, if the second interlayer insulating layer 190 comprises SiN, the second interlayer insulating layer 190 may have a thickness of 2000 to 20000 Å.

If the thickness of the second interlayer insulating layer 190 is less than 2000 Å, it is difficult to secure an insulation property due to a small thickness. In addition, there is a problem with protection of an underlying layer against penetration of external moisture or chemical due to the small thickness.

If the thickness of the second interlayer insulating layer 190 exceeds 20000 Å, it is difficult to perform selective etching on the second interlayer insulating layer 190 by means of formation of a photoresist pattern. That is, the photoresist pattern serves as an etching mask in the etching process, and the photoresist pattern is also etched along with the selective etching of the second interlayer insulating layer 190 due to the excessive thickness of the second interlayer insulating layer 190. If the thickness of the second interlayer insulating layer 190 is excessive, the photoresist pattern may be removed before the selective etching of the second interlayer insulating layer 190 is completed, resulting in a problem of etching performed at an undesired position.

The second interlayer insulating layer 190 may have an inclination angle (f) of 10 to 60 degrees with respect to the surface of the fourth upper electrode 184 or first lower electrode 151 which is exposed therebelow.

If the inclination angle (f) of the second interlayer insulating layer 190 is less than 10 degrees, the substantial area of the fourth upper electrode 184 or first lower electrode 151 that has been exposed decreases. If the area of the exposed portion is increased to secure the substantial area, there is a problem in that an insulation property cannot be secured due to a small inclination angle.

If the inclination angle (f) of the second interlayer insulating layer 190 exceeds 60 degrees, the quality of another layer to be formed on the second interlayer insulating layer 190 may be deteriorated due to a steep profile or slope, or cracks may be produced in the layer. In addition, in a light-emitting operation according to continuous supply of power, properties of the light emitting diode are deteriorated.

FIG. 25 is a plan view showing that first and second pads are formed in the structure of FIG. 20.

Referring to FIG. 25, the first pad 210 may be formed over the first and second cell regions 161 and 162. Accordingly, the first pad 210 can be electrically connected to the first lower electrode 151 in the first cell region 161, which is exposed in FIG. 20.

Moreover, the second pad 220 is formed to be spaced apart from the first pad 210 at a predetermined distance, and may be formed over the third and fourth cell regions 163 and 164. The second pad 220 is electrically connected to the fourth upper electrode 184 in the fourth cell region 164, which is exposed in FIG. 20.

FIG. 26 is a sectional view taken along line B1-B2 in the plan view of FIG. 25, FIG. 27 is a sectional view taken along line C1-C2 in the plan view of FIG. 25, FIG. 28 is a sectional view taken along line D1-D2 in the plan view of FIG. 25, and FIG. 29 is a sectional view taken along line E1-E2 in the plan view of FIG. 25.

Referring to FIG. 26, the first pad 210 is formed over the first and second cell regions 161 and 162. The first pad 210 is formed on the first lower electrode 151 exposed in the first cell region 161, and on the second interlayer insulating layer 190 in the other cell regions. Thus, the first pad 210 is electrically connected to the second semiconductor layer 131 in the first cell region 161 through the first lower electrode 151.

Referring to FIG. 27, the first pad 210 is formed in the second cell region 162, and the second pad 220 is formed to be spaced apart from the first pad 210 in the third cell region 163. The electrical contact of the first or second pad 210 or 220 with the lower or upper electrode is blocked in the second and third cell regions 162 and 163.

Referring to FIG. 28, the second pad 220 is formed over the third and fourth cell regions 163 and 164. Particularly, the second pad 220 is electrically connected to the fourth upper electrode 184 opened in the fourth cell region 164. Thus, the second pad 220 is electrically connected to the first semiconductor layer 114 in the fourth cell region 164.

Referring to FIG. 29, the second pad 220 is formed in the fourth cell region 164, and the first pad 210 is formed to be spaced apart from the second pad 220 in the first cell region 161. The first pad 210 is formed on the first lower electrode 151 in the first cell region 161 and electrically connected to the second semiconductor layer 131.

FIG. 30 is a perspective view taken along line C2-C3 in the plan view of FIG. 25.

Referring to FIG. 30, the first semiconductor layer 113 in the third cell region 163 is electrically connected to the third upper electrode 183. The third upper electrode 183 shields the space between the third and fourth cell regions 163 and 164 and is electrically connected to the fourth lower electrode 154 in the fourth cell region 164. The first and second pads 210 and 220 are spaced apart from each other and formed on the second interlayer insulating layer 190. Of course, as described above, the first pad 210 is electrically connected to the second semiconductor layer 131 in the first cell region 161, and the second pad 220 is electrically connected to the first semiconductor layer 111 in the fourth cell region 164.

Each of the first and second pads 210 and 220 may have a first layer comprising Ti, Cr or Ni and a second layer comprising Al, Cu, Ag or Au formed thereon. The first and second pads 210 and 220 may be formed using a lift-off process. They may be formed by forming a double- or single-layered metal film, forming a pattern through a conventional photolithography process, and then performing dry or wet etching using the pattern as an etching mask. However, an etchant used in the dry or wet etching may vary depending on the material of metal to be etched.

Accordingly, the first and second pads 210 and 220 can be simultaneously formed in one process.

A pad barrier layer (not shown) made of a conductive material may be formed on the first pad 210 or second pad 220. The pad barrier layer is provided to prevent diffusion of metal, which may occur in a bonding or soldering process for the pads 210 and 220. For example, in the bonding or soldering process, tin atoms contained in a bonding metal or soldering material are diffused into the pads 210 and 220, thereby preventing an increase in resistivity of the pads. To this end, the pad barrier layer may be configured with a layer of Cr, Ni, Ti, W, TiW, Mo, Pt or a composite thereof.

Referring to the modeling of FIG. 19, the first semiconductor layers 111, 112, 113 and 114 in the respective cell regions are modeled as n-type semiconductors, and the second semiconductor layers 131, 132, 133 and 134 in the respective cell regions are modeled as p-type semiconductors. The first lower electrode 151 formed on the second semiconductor layer 131 in the first cell region 161 is modeled as the anode electrode of the first light emitting diode D1. Thus, the first pad 210 can be modeled as wiring connected to the anode electrode of the first light emitting diode D1. The fourth upper electrode 184 electrically connected to the first semiconductor layer 114 in the fourth cell region 164 is modeled as the cathode electrode of the fourth light emitting diode D4. Thus, the second pad 220 can be modeled as wiring connected to the cathode electrode of the fourth light emitting diode D4.

Accordingly, an array structure in which the four light emitting diodes D1 to D4 are connected in series formed, and electrical connection thereof to the outside is achieved through the two pads 210 and 220 formed on the single substrate 100.

In particular, referring to FIG. 19, the first lower electrode 152 of the first light emitting diode D1 connected to the positive power voltage V+ is electrically connected to the first pad 210, and the fourth upper electrode 184 of the fourth light emitting diode D4 connected to the negative power voltage V− is electrically connected to the second pad 220.

In the present invention, there is shown that four light emitting diodes are formed while being separated from one another and an anode terminal of one of the light emitting diodes is electrically connected to a cathode terminal of another of the light emitting diodes through the lower and upper electrodes. However, the four light emitting diodes in this embodiment are merely an example, and various numbers of light emitting diodes may be formed.

FIG. 31 is a circuit diagram obtained by modeling a connection of ten light emitting diodes in series according to an embodiment of the present invention.

Referring to FIG. 31, ten cell regions 301 to 310 are defined using the process shown in FIG. 5. A first semiconductor layer, an active layer, a second semiconductor layer and a lower electrode in each of the cell regions 301 to 310 are separated from those in other cell regions. The respective lower electrodes are formed on the second semiconductor layers so as to form anode electrodes of light emitting diodes D1 to D10.

Subsequently, a first interlayer insulating layer and upper electrodes are formed using the processes shown in FIGS. 6 to 17. The formed upper electrodes shield the space between adjacent cell regions, and serve as wiring for achieving electrical connection between anode electrodes of adjacent light emitting diodes.

Furthermore, a second interlayer insulating layer is formed using the processes shown in FIGS. 20 to 29. The lower electrode of the first light emitting diode D1 that is the input light emitting diode connected to a positive power voltage V+ on a current path is exposed, and the upper electrode of the tenth light emitting diode D10 that is an output light emitting diode connected to a negative power voltage V− on the current path is opened. Then, a first pad 320 is formed and connected to the anode terminal of the first light emitting diode D1, and a second pad 330 is formed and connected to a cathode terminal of the tenth light emitting diode D10.

The other light emitting diodes are connected in series/parallel so as to form an array.

FIG. 32 is a circuit diagram obtained by modeling an array having light emitting diodes connected in series/parallel according to an embodiment of the present invention.

Referring to FIG. 32, a plurality of light emitting diodes D1 to D8 are connected in series and/or in parallel to one another. The light emitting diodes D1 to D8 are formed independently of one another through the definitions of cell regions 401 to 408. As described above, an anode electrode of each of the light emitting diode D1 to D8 is formed through a lower electrode. Wiring between a cathode electrode of each of the light emitting diodes D1 to D8 and the anode electrode of an adjacent light emitting diode is made by forming an upper electrode and performing an appropriate wiring process. However, the lower electrode is formed on a second semiconductor layer, and the upper electrode is formed to shield the space between adjacent cell regions.

Finally, a first pad 410 supplied with a positive power voltage V+ is electrically connected to the lower electrode formed on the second semiconductor layer of the first or third light emitting diode D1 or D3, and a second pad 420 supplied with a negative power voltage V− is electrically connected to the upper electrode that is a cathode electrode of the sixth or eighth light emitting diode D6 or D8.

Thus, in FIG. 32, the input light emitting diode corresponds to the first and third light emitting diodes D1 and D3, and the output light emitting diode corresponds to the sixth and eighth light emitting diodes D6 and D8.

According to the present invention described above, light generated in the active layer of each of the light emitting diodes is reflected from the lower and upper electrodes toward the substrate, and the flip-chip type light emitting diodes are electrically connected through wiring of the upper electrodes on a single substrate. The upper electrode is shielded from the outside through the second interlayer insulating layer. The first pad supplied with a positive power voltage is electrically connected to a lower electrode of a light emitting diode connected most closely to the positive power voltage. The second pad supplied with a negative power voltage is electrically connected to an upper electrode of a light emitting diode connected most closely to the negative power voltage.

Thus, it is possible to solve inconvenience in a process of mounting a plurality of flip-chip type light emitting diodes on a submount substrate and implementing two terminals to an external power source through wiring arranged on the submount substrate. In addition, the space between adjacent cell regions can be shielded by the upper electrode, thereby maximizing the reflection of light toward the substrate.

Further, the second interlayer insulating layer protects a laminated structure, which is arranged between the substrate and the second interlayer insulating layer, from external temperature or humidity and the like. Thus, it is possible to implement a structure that can be directly mounted on a substrate without intervention of any separate packaging means.

In particular, since a plurality of flip-chip type light emitting diodes are implemented on a single substrate, there is an advantage in that a commercial power source can be directly used while excluding a voltage drop, a conversion of voltage level or a conversion of waveform for the commercial power source.

Although the present invention has been described in connection with the preferred embodiments, those implementations are examples of the disclosed technology and other implementations are also possible. Accordingly, it will be understood by those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the invention defined by the appended claims. 

The invention claimed is:
 1. A light emitting diode array, comprising: a substrate; a plurality of light emitting diodes arranged over the substrate, each of the plurality of light emitting diodes including a first semiconductor layer, an active layer and a second semiconductor layer; a plurality of upper electrodes of a common material arranged over the plurality of light emitting diodes, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes and insulated from the second semiconductor layer of the respective one of the light emitting diodes by a first insulating layer positioned at least partially below each of the plurality of upper layer electrodes; and first and second pads arranged over the upper electrodes, wherein at least one of the upper electrodes electrically connected to a given one of the light emitting diodes is electrically connected to the second semiconductor layer of another light emitting diode adjacent to the given light emitting diode, wherein the light emitting diodes are electrically connected in series by the upper electrodes, wherein the first pad is electrically connected to at least one of the light emitting diodes at a power input region, and wherein the second pad is electrically connected to at least one of the light emitting diodes at a power output region; and further comprising lower electrodes arranged over the second semiconductor layers of the light emitting diodes, wherein the first interlayer insulating layer is disposed partially over the lower electrodes.
 2. The light emitting diode array of claim 1, wherein each of the first and second pads is positioned over at least two of the light emitting diodes.
 3. The light emitting diode array of claim 2, wherein the first and second pads are formed of a common material to be positioned on the same level.
 4. The light emitting diode array of claim 3, wherein each of the first and second pads comprises: a first layer comprising Ti, Cr or Ni; and a second layer formed over the first layer and comprising Al, Cu, Ag or Au.
 5. The light emitting diode array of claim 4, wherein the first or second pad further comprises a pad barrier layer including a conductive material.
 6. The light emitting diode array of claim 5, wherein the pad barrier layer comprises a layer including Cr, Ni, Ti, W, TiW, Mo, Pt, or a composite thereof.
 7. The light emitting diode array of claim 2, wherein the upper electrodes are insulated from side surfaces of the light emitting diodes by the first interlayer insulating layer.
 8. The light emitting diode array of claim 7, wherein the first interlayer insulating layer leaves a portion of the lower electrodes on the light emitting diodes exposed, and wherein at least one of the upper electrodes is configured to electrically connect in series two adjacent ones of the light emitting diodes, the at least one of the upper electrodes electrically connected to the first semiconductor layer of one of the two adjacent light emitting diodes and electrically connected to the second semiconductor layer and the exposed portion of the lower electrode of the other of the two adjacent light emitting diodes.
 9. The light emitting diode array of claim 8, wherein each of the lower electrodes comprises a reflective layer.
 10. The light emitting diode array of claim 8, further comprising a second interlayer insulating layer arranged over the upper electrodes, wherein the second interlayer insulating layer is arranged at least partially over the upper electrodes to expose the lower electrode arranged over the second semiconductor layer of one of the light emitting diodes, and the upper electrode electrically connected to the first semiconductor layer of another light emitting diode, and wherein each of the first and second pads is connected to the lower and upper electrodes through the second interlayer insulating layer.
 11. The light emitting diode array of claim 1, wherein each of the light emitting diodes has a via hole exposing the first semiconductor layer, and wherein at least one of the upper electrodes is electrically connected to the first semiconductor layer exposed by the via hole.
 12. The light emitting diode array of claim 1, wherein the upper electrodes occupy at least 30% and less than 100% of the entire area of the light emitting diode array.
 13. The light emitting diode array of claim 1, wherein each of the upper electrodes is in the form of a plate or sheet having a ratio of length to width in a range of 1:3 to 3:1.
 14. The light emitting diode array of claim 1, wherein at least one of the upper electrodes has a size greater than that of one of the light emitting diodes.
 15. The light emitting diode array of claim 1, wherein each of the light emitting diodes is separated by a mesa-etched region exposing the substrate, and side surfaces of the light emitting diodes exposed by mesa etching have an inclination angle of 10 to 60 degrees with respect to the substrate.
 16. The light emitting diode array of claim 15, wherein each of the light emitting diodes has a via hole exposing a portion of the first semiconductor layer, and each of the upper electrodes is connected to the first semiconductor layer of a corresponding light emitting diode through the via hole.
 17. The light emitting diode array of claim 16, wherein the inclination angle of the sides of the layers exposed through the via hole is in a range of 10 to 60 degrees.
 18. The light emitting diode array of claim 15, further comprising a first interlayer insulating layer arranged between the light emitting diodes and the upper electrodes, wherein the sides surfaces of the upper electrodes have an inclination angle of 10 to 45 degrees with respect to a surface of the first interlayer insulating layer.
 19. The light emitting diode array of claim 18, wherein the upper electrodes have a thickness in a range of 2000 to 10000 Å.
 20. The light emitting diode array of claim 18, further comprising lower electrodes arranged over the second semiconductor layers of the light emitting diodes, wherein the first interlayer insulating layer exposes a portion of the lower electrodes on the light emitting diodes, and wherein at least one of the upper electrode is electrically connected to the exposed portion of a corresponding one of the lower electrodes.
 21. The light emitting diode array of claim 20, wherein the thickness of the lower electrodes is in a range of 2000 to 10000 Å.
 22. The light emitting diode array of claim 20, wherein the side surfaces of the first interlayer insulating layer have an inclination angle of 10 to 60 degrees with respect to a surface of the exposed lower electrode.
 23. The light emitting diode array of claim 22, wherein the first interlayer insulating layer has a thickness of 2000 to 20000 Å.
 24. The light emitting diode array of claim 20, further comprising a second interlayer insulating layer arranged over the upper electrodes, wherein the second interlayer insulating layer is arranged at least partially over the upper electrodes to expose the lower electrode arranged over the second semiconductor layer of one of the light emitting diodes, and the upper electrode connected to the first semiconductor layer of another light emitting diode, and wherein each of the first and second pads is connected to the lower and upper electrodes through the second interlayer insulating layer.
 25. The light emitting diode array of claim 24, wherein the side surface of the second interlayer insulating layer has an inclination angle of 10 to 60 degrees with respect to a surface of the upper electrode.
 26. The light emitting diode array of claim 24, wherein the second interlayer insulating layer has a thickness of 2000 to 20000 Å.
 27. A light emitting diode array, comprising: a substrate; a plurality of light emitting diodes arranged over the substrate, each of the plurality of light emitting diodes including a first semiconductor layer, an active layer and a second semiconductor layer; a plurality of lower electrodes arranged over the second semiconductor layers of the light emitting diodes; a plurality of upper electrodes arranged over the plurality of light emitting diodes, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes; and first and second pads arranged over the upper electrodes, wherein at least one of the upper electrodes electrically connected to a given one of the light emitting diodes is electrically connected to the second semiconductor layer of another light emitting diode adjacent to the given light emitting diode through an exposed portion of the lower electrode of another light emitting diode, wherein the light emitting diodes are electrically connected in series by the upper electrodes, and wherein the sides surfaces of the lower electrodes have an inclination angle of 10 to 45 degrees with respect to a surface of the second semiconductor layer. 